General Description
Slave serial interface compatible with the popular SPI™ standard. Permits an SPI Master to communicate with your FPGA, ASIC or SoC. The SPI Slave supports up to 512 custom registers that are accessible using a set of simple SPI read and write commands.
Key Design Features
– Fully SPI compliant
– Simple command interface
– Configurable number of 8-bit config registers (max 256)
– Configurable number of 8-bit status registers (max 256)
– Configurable clock polarity (CPOL)
– Configurable clock phase (CPHA)
– Typical FPGA comms up to 50 Mbits/s
Applications
– Inter-chip board-level communications
– Simple method to add SPI-accessible control registers to your FPGA, ASIC or SoC
– Serial comms at higher data rates than other protocols such as UART, I2C and USB1.x
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