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Signal synchronization block

– Input power: +5V DC, +12V DC
– Output signal: Pulse signal, CMOS, amplitude level 0 ÷ 5 V
– Input signal: Pulse signal, CMOS, amplitude level 0 ÷ 5 V
– Data input and output: using TCP/IP protocol, communication via LAN at 1 Gbps speed
– Processor chip: Virtex 6 FPGAs or equivalent, supporting LAN communication at speeds of 10-100-1000 Mbps Ethernet. I/O can be expanded with the FPGA Mezzanine Card (FMC) communication standard.
– Operating temperature: -45 ÷ 85 °C
– The circuit boards are coated with conformal, anti-oxidation
– Withstand vibration with vibration frequency: (10 ÷ 300) Hz; vibration acceleration: 3 g; Vibration amplitude: 2 mm; Vibration time: 30 minutes;
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