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Request signal decoding and response signal generation function module
- Model: DRM89-22HV
- Programming languages: VHDL, Verilog
- Parameter interface, control:
- System synchronous clock frequency: ≥ 50 MHz
- ROM memory capacity: ≥ 100 Kb
- Number of 18×18 multipliers: ≥ 15
- Number of Logic Elements (LE): ≥ 15000
- Block RAM capacity: ≥ 1200 Kb
- Synchronous pulse group decoding unit: Input signal parameters:
- Amplitude: (2.5÷5) V
- Pulse width: (0.5±0.05) µs
- Number of pulses: 4
- Interval between pulses relative to the first pulse: (3; 9; 12) µs or (3; 6; 12) µs Output signal parameters:
- Amplitude: (2.5÷5) V
- Pulse width: (0.5±0.05) µs
- Position relative to the first input pulse: (12±0.1) µs
- Priority signal response signal generator: Input pulse parameters:
- Amplitude: (2.5÷5) V
- Pulse width: (0.7÷1.2) µs
- Data cancellation speed upon priority signal: ≤ 9 µs
- Signal sequence code writing unit: Input pulse parameters:
- Amplitude: (2.5÷5) V
- Pulse width: (0.35÷0.7) µs
- Serial-to-parallel conversion bit count: 45 bits
- Response pulse signal generator: Busy processing and frequency code order pulse parameters:
- Busy processing and frequency code order pulse width 1: (105±0.1) µs
- Busy processing and frequency code order pulse width 2: (108±0.7) µs Signal parameters determining frequency code position:
- Number of pulse positions: 9
- Interval between the first and second pulses: (6±0.1) µs
- Interval between the second pulse and subsequent pulses: (3±0.1) µs
